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DATA SHEET
O K I N E T W O R K P R O D U C T S
ML53612 64-Channel Full Duplex H.100/H.110 CT Bus System Interface and Time-Slot Interchange
January 2000
Revision History September 1999 January 2000 320138-001 320138-002 Initial Release Timing tables altered on page 53: "Local Clock and Frame Synchronization Timing", "Local Clock to CT Bus Clock Skew", and "Local Serial Stream Timing" Timing diagram (Figure 11) atered on page 54: "Local Clock and Frame Synchronization Timing"
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Contents
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ML53612 176-Pin LQFP Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 CT Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Test Access Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Pin Continuity Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Analog PLL Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Microprocessor Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Analog PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Slave PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Master PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Reference Master . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Local Clock and Frame Sync . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Local Streams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 CT Bus Streams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 CT_D disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Diagnostic Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 GPIO Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Message Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Law/Linear Conversion & Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Microprocessor Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Command/Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Internal Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Device ID Registers (Read Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Stream Switch Routing Registers, AR = 1007h:1000h (Ch. 7:0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Stream Switch Connection Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Transmit Switch Routing Registers, AR = 203fh:2000h (Ch. 63:0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Receive Switch Routing Registers, AR = 303fh:3000h (Ch. 63:0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Indirect Transmit Switch Parallel Access Registers, AR = 403fh:4000h (Ch. 63:0) . . . . . . . . . . . . . . . . . . . . 46 Indirect Receive Switch Parallel Access Registers, AR = 503fh:5000h (Ch. 63:0) . . . . . . . . . . . . . . . . . . . . 46 Transmit Switch Conversion Registers, AR = 603Fh:6000h (Ch. 63:0) Receive Switch Conversion Registers, AR = 703Fh:7000h (Ch. 63:0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 H.100/H.110 Bus Timing Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Clock Skew Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 ML53612 Package specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 LQFP176 Package Outlines and Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 LQFP176 Mounting Pad Reference Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
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ML53612
H.100/H.110CT Bus System Interface and Time-Slot Interchange 1.0 DESCRIPTION
The ML53612 is a complete CT Bus system interface and time-slot interchange device that provides a cost-effective connection between a computer board's telephony interfaces or signal processing resources and the CT Bus. The ML53612 is an evolution of existing time-slot interchange ICs which offers seamless interoperability with SCbus devices. A key element in computer telephony (CT) equipment is the auxiliary telecom bus. Most manufacturers of high-capacity CT equipment have used one or more types of telecom buses to transport and switch low-latency communications traffic between boards within the computer, bypassing the computer's main I/O and memory buses. To simplify the integration of devices that incorporate a telecom bus, the Enterprise Computer Telephony Forum (ECTF) developed a standard bus (H.100/H.110 CT BusTM) that provides compatibility modes with the most prevalent telecom buses today (SCbusTM and MVIP-90TM), as well as the capacity and feature set needed to support the next generation of high capacity CT servers. The new CT Bus is embraced by Dialogic under the Signal Computing System ArchitectureTM (SCSATM) umbrella of open standards for building interoperable CT systems. The ML53612 runs in both 4 MHz and 8 MHz SCbus modes and supports the switching features needed to integrate CT Bus devices with 4 MHz SCbus, 8 MHz SCbus, and 2 MHz MVIP-90 devices. Because the H.100/H.110 CT Bus uses an identical switching model and clock speeds to that used for the SCbus, developers have unparalleled flexibility in integrating these two types of devices, or in transitioning from one type to the other. The ML53612 takes full advantage of the mandatory and optional features defined in the ECTF H.100 and H.110 interoperability specifications. It is a non-blocking 128 x 4096 time-slot switch, interfacing up to 128 ports on its parent device to any of the 4096 time-slots on the new CT Bus. The number of local time-slots available makes it easier to design low- to medium-density CT hardware, supporting up to two network interfaces or 64 voice processing ports per chip. This powerful chip is offered in an ultra slim profile (176-pin LQFP package, with a 24 mm x 24 mm x 1.4 mm body size) that makes it possible to mount the chip on either side of the board. The chip is fully software programmable, and can be controlled by a variety of microprocessors, including Intel and Motorola in both multiplexed and nonmultiplexed modes.
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1.0 FEATURES
* High functionality, low cost implementation of the ECTF H.100/H.110 interoperability specifications. * Simple to connect PCI and cPCITM board-level circuitry to the universally accepted CT BusTM. * Ultra slim profiling (176-pin LQFP package). * Up to 128 programmable connections (64 transmit and 64 receive) to any of the 4096 timeslots on the H.100/H.110 CT Bus. * 8-channel stream-to-stream switching for data stream connections at variable rates. * Implementation of all compatibility signals for complete interoperability with existing 4 MHz SCbusTM, 8 MHz SCbus, 2 MHz MVIP-90TM devices, and H-MVIPTM. * Master PLL meets AT&T 62411 MTIE and jitter attenuation requirements to provides reliable clock synchronization for network-grade connection to digital network interfaces. * Supports all H.100/H.110 CT Bus clock fallback features. * Choice of constant or minimum switching delay on a per time-slot basis. * 3.3 V I/O with 5 V tolerant input. * Supports multiplexed and nonmultiplexed address/data bus modes for both Intel and Motorola microprocessors. * Supports CT Bus optional message channel interface, for both H.100 (PCI) and H.110 (cPCI) applications. * Supports a variety of framing formats via a configurable local bus. * Efficient microprocessor interface access to Local and CT Bus data streams through direct parallel access to/from transmit and receive switch. * Direct Parallel Access to/from Transmit and Receive switch allows efficient microprocessor interface access to local and CT Bus data streams.
1.1 Applications * * * * * * Low- to medium-density computer telephony hardware (PCI and cPCI platforms) Enhanced service platforms Private branch exchanges (PBXs) Wireless base stations Internet telephony systems Digital trunking equipment
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2.0 PIN CONFIGURATION
132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176
88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
Figure 1. ML53612 176-Pin LQFP Pin Configuration
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2.1 ML53612 176-Pin LQFP Pin Assignment [1]
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 Pin Name VDDC ALE VDDO CS_N RD_N WR_N VSSO RESET I_N INT VDDO D_0 A_0 D_1 A_1 VSSO D_2 A_2 D_3 A_3 VDDO D_4 A_4 D_5 A_5 VSSO Pin 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 Pin Name D_6 A_6 D_7 A_7 NC NC NC VDDO L_NETREF_0 L_NETREF_1 NC NC VSSO NC NC NC NC VSSC VDDC VDDO APLL_VDDO APLL_VDDC APPL_PC APPL_VCO APPL_VSSC APLL_VSSO Pin 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 Pin Name VSSO APLL_TEST TMS TCK TRST_N TDI TDO VDDO MC_TXD MC_RXD MC_CLK VSSO C16_NEG_N C16_POS_N VDDO C4_N C2 VSSO SCLKX2_N SCLK VDDO FR_COMP_N CT_MC VSSO CT_C8_B Pin 79 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 Pin Name VDDO VSSO CT_NETREF_2 CT_NETREF_1 VDDO CT_C8_A VSSO VSSC VDDC CT_D_0 VDDO CT_D_1 CT_D_2 VSSO CT_D_3 CT_D_4 VDDO CT_D_5 VSSO CT_D_6 VDDO CT_D_7 CT_D_8 VSSO Pin 105 107 108 109 110 111 112 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 Pin Name CT_D_9 CT_D_10 VDDO CT_D_11 VSSO CT_D_12 CT_D_13 VDDO CT_D_14 VSSO CT_D_15 CT_D_16 VDDO CT_D_17 CT_D_18 VSSO CT_D_19 VDDO CT_D_20 VSSO CT_D_21 CT_D_22 VDDO CT_D_23 CT_D_24 VSSO Pin 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 Pin Name CT_D_25 VSSC VDDC CT_D_26 VDDO CT_D_27 VSSO CT_D_28 CT_D_29 VDDO CT_D_30 CT_D_31 VSSO GPIO_0 GPIO_1 VDDO GPIO_2 GPIO_3 VSSO L_SI_0 L_SI_1 NC NC VDDO NC NC Pin 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 NC NC VSSO L_SO_0 L_SO_1 NC NC VDDO NC NC NC NC VSSO L_CLK_0 L_FS_0 L_CLK_1 L_FS_1 CT_D_DISABLE TEST VSSC Pin Name
APPL_CLKREF 80
CT_FRAME_B_N 106
CT_FRAME_A_N 113
1. In this document, signals ending with "_N" are "active low" (eg. CS_N). Note that in the H.100/H110 specification, active low is indicated with a preceding forward slash (eg. /CS).
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3.0 SIGNAL DESCRIPTIONS
Signal Description [1]
Name D_[7:0] A_ [7:0] ALE (AS) CS_N RD_N (STRB_N) WR_N (R/W_N) RESET I_N (M) CT_D_DISABLE L_NETREF_[1:0] L_SI_[1:0] MC_TXD APLL_CLKREF APLL_VDDO APLL_VDDC APLL_PC APLL_VCO APLL_VSSC APLL_VSSO APLL_TEST TEST TMS TCK TRST_N TDI INT CT_D_[31:0] CT_FRAME_A_N CT_C8_A CT_NETREF_1 CT_NETREF_2 CT_FRAME_B_N CT_C8_B CT_MC Description Microprocessor Data Bus. (I/O, TTL Schmitt, 8 mA, 5V tolerant) Microprocessor Address Bus. (Input, TTL Schmitt, 5V tolerant) Intel Bus Mode - Address Latch Enable. Motorola Bus Mode - Address Strobe. The Microprocessor Address Bus A[9:0] is latched internally on the falling edge of this signal. (Input, TTL Schmitt, 5V tolerant) Chip Select. This active low signal selects the ML53612 for a microprocessor read or write operation. (Input, TTL Schmitt, 5V tolerant) Intel Bus Mode - Microprocessor Bus Read. Motorola Bus Mode - Microprocessor Bus Strobe. (Input, TTL Schmitt, 5V tolerant) Intel Bus Mode - Microprocessor Bus Write. Motorola Bus Mode - Microprocessor Bus Read/Write signal. (Input, TTL Schmitt, 5V tolerant) Reset. This active high input signal initializes the microprocessor interface, configuration, and routing registers. (Input, TTL Schmitt, 5V tolerant) Microprocessor Bus Mode. When this input is low, Intel Bus Mode is selected. When this input is high, Motorola Bus Mode is selected. (Input, TTL Schmitt, 5V tolerant) CT_D Global disable. (I/O, TTL Schmitt, 8 mA, 50 k Pull Up, 5V tolerant) Local Network Reference [1:0] Input. (Input, TTL Schmitt, 50 k Pull Up, 5V tolerant) Local bus Serial Input Data Input. (Input, TTL Schmitt, 50 k Pull Up, 5V tolerant) Message Channel Transmit Data Input. (Input, TTL Schmitt, 50 k Pull Up, 5V tolerant) Analog PLL Clock Reference Input. (Input, TTL Schmitt, 50 k Pull Up, 5V tolerant) +3.3 Volt Analog PLL I/O Power Supply +3.3 Volt Analog PLL Core Power Supply Analog PLL Phase Comparator Analog Output Analog PLL VCO Analog Input Analog PLL Core Ground Analog PLL I/O Ground Analog PLL Test Enable Input. (Input, TTL Schmitt, 50 k Pull Up, 5V tolerant) Test Select. This input enables the pin continuity test. (Input, TTL Schmitt, 50 k Pull Up, 5V tolerant) Test Access Port Mode Select. (Input, TTL Schmitt, 50 k Pull Up, 5V tolerant) Test Access Port Clock. (Input, TTL Schmitt, 50 k Pull Up, 5V tolerant) Test Access Port Reset. (active low). (Input, TTL Schmitt, 50 k Pull Up, 5V tolerant) Test Access Port Data Input. (Input, TTL Schmitt, 50 k Pull Up, 5V tolerant) Interrupt Output. (I/O, TTL Schmitt, 50 k Pull Up, 8 mA, 5V tolerant) CT Bus Serial Data Streams. (I/O, PCI, 5V tolerant) CT Bus "A" Frame Sync. (I/O, TTL Schmitt, 24 mA, 5V tolerant) CT Bus "A" 8 MHz Clock. (I/O, TTL Schmitt, 24 mA, 5V tolerant) CT Bus Network Reference 1. (I/O, PCI, 5V tolerant) CT Bus Network Reference 2. (I/O, PCI, 5V tolerant) CT Bus "B" Frame Sync. (I/O, TTL Schmitt, 24 mA, 5V tolerant) CT Bus "B" 8 MHz Clock. (I/O, TTL Schmitt, 24 mA, 5V tolerant) CT Bus Message Channel. (I/O, TTL Schmitt, 24 mA, 5V tolerant)
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Signal Description [1]
Name FR_COMP_N SCLK SCLKX2_N C2 C4_N C16_POS_N C16_NEG_N L_CLK_1 L_FS_1 L_CLK_0 L_FS_0 L_SO_[1:0] MC_CLK MC_RXD GPIO_[3:0] TDO NC VDDO VSSO VDDC VSSC Description Compatibility frame sync used by SCbus, MVIP-90, and H-MVIP. (I/O, TTL Schmitt, 24 mA, 5V tolerant) SCbus Clock. (I/O, TTL Schmitt, 24 mA, 5V tolerant) SCbus X2 Clock. (I/O, TTL Schmitt, 24 mA, 5V tolerant) MVIP-90 2.048 MHz Clock. (I/O, TTL Schmitt, 6 mA, 5V tolerant) MVIP-90 4.096 MHz Clock. (I/O, TTL Schmitt, 6 mA, 5V tolerant) H-MVIP 16.384 MHz Positive active low Clock. High to low transition on frame boundary. (I/O, TTL Schmitt, 24 mA, 5V tolerant) H-MVIP 16.384 MHz Negative active low Clock. Low to high transition on frame boundary. (I/O, TTL Schmitt, 24 mA, 5V tolerant) Local bus Clock 1. (I/O, TTL Schmitt, 24 mA, 50 k Pull Up, 5 V tolerant) Local bus Frame Sync 1. (I/O, TTL Schmitt, 24 mA, 50 k Pull Up, 5V tolerant) Local bus Clock 0. (I/O, TTL Schmitt, 24 mA, 50 k Pull Up, 5 V tolerant) Local bus Frame Sync 0. (I/O, TTL Schmitt, 50 k Pull Up, 24 mA, 5V tolerant) Local bus Serial Output Data Streams. (I/O, TTL Schmitt, 50 k Pull Up, 8 mA, 5V tolerant) Message Channel Clock Output. (I/O, TTL Schmitt, 50 k Pull Up, 6 mA, 5V tolerant) Message Channel Receive Data Output. (I/O, TTL Schmitt, 50 k Pull Up, 6 mA, 5V tolerant) General Purpose I/O ports. (I/O, TTL Schmitt, 24 mA, 50 k Pull Up, 5V tolerant) Test Access Port Data Output. (Output, 6 mA, 5V tolerant) No Connect +3.3 Volt I/O Power Supply I/O Ground +3.3 Volt Core Power Supply Core Ground
1. Signals ending in "_N" are active low.
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4.0 FUNCTIONAL DESCRIPTION
The ML53612 has the following interfaces:
* * * *
Microprocessor Interface Local Serial Data In Local Serial Data Out Local Timing
* Analog PLL Reference Clock * CT Bus Timing * CT Bus Serial Data
Microprocessor Interface
Configuration & Routing Register Internal Control
8 Channel Stream Switch 64 x 4096 Transmit Switch Local Connect
Local Serial Data In
64-Channel Transmit Conversion
CT Bus Serial Data
Local Serial Data Out
64-Channel Receive Conversion
4160 x 64 Receive Switch Internal Timing Slave Digital PLL Master Digital PLL Analog PLL 131.072 MHz CT Bus Timing
Local Timing
APLL Reference Clock
Figure 2. Block Diagram 4.1 Local Bus The local bus consists of up to two serial input ports and two serial output ports, totalling 128 possible local bus connections to the CT Bus. The input and output ports can be configured independently as two 2 Mbps streams, one 4 Mbps stream, or one-half of an 8 Mbps stream. The chip includes two independent, configurable local clock and frame synchronization signals. The local clocks have configurable polarity and frequency that can be set to 2 MHz, 4 MHz, 8 MHz, or 16 MHz regardless of local stream data rate. The local frame syncs also have a configurable polarity and can be set to use one of three framing formats (early, straddle, or late). To transfer data to and from the local bus, the ML53612 allows the user to select a minimum delay or constant delay buffer mode on a per channel basis. In the minimum delay mode, the input-output buffer transfer occurs on the next 2 Mbps time-slot boundary, reducing any potential channel delay for classic voice processing applications. In the constant delay mode, the buffer transfer occurs at the frame boundary for bundling and proper switching of wide-band data, for data sent on the ISDN H channel.
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4.2 CT Bus The ML53612 provides access to all 4096 CT Bus time-slots. The upper 16 data lines run at 8 Mbps, while the lower 16 data lines can be configured, in groups of four, to run at 8 Mbps, 4 Mbps, or 2 Mbps for compatibility with SCbus and MVIP-90 devices. The chip uses an internal analog phase locked loop (PLL) as a rate multiplier to produce a 131.072 MHz internal clock locked to a variety of reference frequencies. This high frequency internal clock provides fine grained correction steps (7.6 nS) for the master and slave digital PLLs. The main CT Bus network reference signal can be configured to run at 8 kHz, 1.544 MHz, or 2048 MHz. The timing for the CT Bus can be configured to be derived from the local clock and frame sync signals to allow multiple chips to be connected to the CT Bus without overloading the reference clock line. The ML53612 incorporates internal master digital PLL circuitry that is designed to meet the jitter attenuation, holdover and Maximum Time Interval Error (MTIE) requirements of the AT&T 62411 Stratum 3, 4 and 4E. This enables the ML53612 to be well suited for developers of digital telephone network interfaces, where reliable clock synchronization is critical. Because the circuitry is internal, board designers do not have to add expensive or custom circuitry to support these types of environments. The ML53612 also includes an 8-channel stream-to-stream switch to connect one CT Bus data stream to another at the same or different data rates. This type of connection makes it possible for CT Bus compatible devices (such as SCbus and MVIP-90) to efficiently exchange data even though they operate at different rates. This stream switch enables switching between any of the 32 CT Bus data streams operating at 2, 4, or 8 Mbps. Depending upon the data stream rates, the stream switch provides a minimum of 256 and a maximum of 1024 unidirectional time-slot connections. Stream switches in other ML53612 devices, within a system, may be used simultaneously to increase switching capability. 4.3 Test Access Port The ML53612 supports IEEE 1-149.1 Boundary Scan. For Normal operation, the TRST_N pin should be driven low. 4.4 Pin Continuity Test For normal operation, the TEST pin is driven low. When the TEST pin is high, all pins except VDD, VSS, NC, APLL_PC, APLL_VCO, TMS, TCK, TRST_N, TDI, TDO, TEST are sequentially "NAND'ed" with ALE and output on TDO. This test allows each input pin to be toggled and a corresponding output to be observed on the TDO pin to verify the proper connection of the ML53612 to a printed circuit board. 4.5 Analog PLL Test For normal operation, the APLL_TEST pin is driven low. 4.6 Microprocessor Interface Both Intel and Motorola microprocessor bus interfaces are supported. Drive I_N (M) low for Intel mode and high for Motorola mode. Multiplexed addresses are latched on the falling edge of ALE (AS). If multiplexed address is not used, drive ALE (AS) high. Multiplexed address and data must be connected to both A_ and D_ pins.
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4.7 Analog PLL The analog PLL is used to create an internal 131.072 MHz clock locked to one of several reference frequencies. The analog PLL reference signal is input on the APLL_CLKREF pin and should be a stable clock typically 25 ppm. An external loop filter is required (see Figure 3).
R2 100 R1 19 k APLL_PC CI 0.01 F APLL_VCO APLL_VSS
Figure 3. Analog PLL Loop Filter
4.8 Slave PLL The slave PLL is used to generate all of the internal timing for the ML53612. Even when the ML53612 is enabled as master, the slave PLL is still in operation. The slave PLL is a fast tracking digital PLL operating at 131.072 MHz. The slave PLL can be configured to lock to one of the following sources: * * * * * * CT_C8_A and CT_FRAME_A CT_C8_B and CT_FRAME_B SCLK and FR_COMP C2 and FR_COMP L_CLK_0 and L_FS_0 L_CLK_1 and L_FS_1
4.9 Master PLL The master PLL is used to generate timing for the CT Bus. The master PLL is a digital PLL operating at 131.072 MHz. When operating as primary master the PLL can lock to one of two local network references, or one of two CT Bus network references. These reference signals may be 8 kHz, 1.536 MHz, 1.544 MHz or 2.048 MHz. When operating as secondary master the PLL locks to the primary CT Bus master. The master PLL can be configured to automatically switch from secondary to primary in the event of a CT Bus timing error. The master PLL can be configured to drive either the CT Bus "A" or "B" signals as well as all of the compatibility clocks defined in the H.100/H.110 Specifications. When operating as the primary master, the PLL provides jitter attenuation with a cut-off frequency of 1.25 Hz and a roll-off of 20dB per decade. When operating as the secondary master, the PLL is fast tracking. When operating as the primary master, the PLL has a lock range of 488 ppm (minus the tolerance of APLL_CLKREF source). The maximum lock time is 3s. Holdover stability is 0.06 ppm, resulting in a frame slip rate of 42/day, assuming no drift in APLL_CLKREF source, exceeding the AT&T 62411 Stra-
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tum 3 requirement of 255/day. During normal operation new holdover values are updated at 128ms intervals. To make an MTIE compliant reference switch, enable "Condition Master PLL reference", select the "Master PLL Reference", and configure the "Master PLL Mode " to normal.The master PLL will be locked to the selected reference. The following sequence will produce an MTIE-compliant reference switch: 1. Change the "Master PLL Mode" from Normal to Holdover. The master PLL can also be configured to make this change automatically in the event of a master PLL error. 2. Change the "Master PLL Reference Select" to the new reference, or change the reference source of CT_NETREF. 3. Change the "Master PLL Mode" back to Normal. MTIE Specifications
ML53612 MTIE during rearrangement Phase change slope 100 ns 81 ns / 1.326 ms AT&T 62411 Stratum 3 and 4E 1 s 81 ns / 1.326 ms
4.10 Reference Master CT_NETREF_1 and CT_NETREF_2 can be independently configured to output a reference signal to the CT Bus selected from one of two local network reference inputs. The local network references can be passed through or divided by 192, 193, or 256. 4.11 Local Clock and Frame Sync Two sets of local clock and frame sync are provided. A variety of clock frequencies, polarities, and framing formats may be selected to allow "glue less" local port interfacing. Each set of local clock and frame sync may be configured separately. The frequency selection is independent of the local stream rate. 4.12 Local Streams The local streams consist of up to two serial input ports and two serial output ports. The local streams can be configured to operate as two 2 Mbps streams, one 4 Mbps stream, or one-half of an 8 Mbps stream. Local Stream Time-Slot to Channel Mapping
Local stream L_SI_0, L_SO_0 L_SI_1, L_SO_1 8 Mbps stream rate time-slot 63:0 channel 63:0 4 Mbps stream rate time-slot 63:0 channel 63:0 2 Mbps stream rate time-slot 31:0 channel 31:0 channel 63:32
Note: When 8 Mbps stream rate is selected, time-slots 127:64 are not used. 4.13 CT Bus Streams Connection to all 32 CT Bus streams is supported without restriction. The upper 16 streams run at 8 Mbps while the lower 16 may be configured, in groups of four, to operate at 8 Mbps, 4 Mbps, or 2 Mbps.
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4.14 CT_D disable The user may disable all CT_D output streams in the event of a bus timing error. When enabled, an error on the slave PLL reference source causes the CT_D streams to be tri-stated until an entire frame time without errors has passed. The CT_D_DISABLE signal is provided to link multiple ML53612 devices. 4.15 Diagnostic Mode Diagnostic mode tri-states all CT Bus signals while internally looping-back CT Bus outputs to inputs. This mode allows a printed circuit board containing the ML53612 to be thoroughly tested without causing CT Bus errors. 4.16 Interrupts The ML53612 supports the following interrupt sources: * CT Bus A Error * CT Bus B Error CT Bus A (CT Bus B) error is detected when CT_C8_A (CT_C8_B) rising edge does not occur within 35 ns of the expected time, relative to the previous period (see Figure 4) or when CT_FRAME_A_N (CT_FRAME_B_N) low does not occur when expected. (See ECTF H.100/H.110 Specifications for details on CT_C8_(A/B) and CT_FRAME_(A/B)_N signal timing.) * SCbus Error SCbus error is detected when SCLK does not transition at close to the expected frequency (C_[25:24] determines the expected frequency) or FR_COMP_N low does not occur when expected. (See ECTF H.100/H.110 Specifications for details on SCLK, SCLKx2, and FR_COMP_N signal timing.) * MVIP Error MVIP error is detected when C2 does not transition at close to 2 MHz, or FR_COMP_N low does not occur when expected. (See ECTF H.100/H.110 Specifications for details on C2 and FR_COMP_N signal timing). * Master PLL Out of Lock Error Master PLL error is detected when the master PLL is not locked to the selected Reference defined by C_[43:40]. * Frame Boundary Frame Boundary interrupt is not an error condition, and occurs when the internal state machine crosses a frame boundary. * GPIO GPIO interrupt occurs when one or more of the GPIO inputs match the programmed latch polarity, defined by C_[167:136]. The interrupts are both globally and individually maskable, and are signaled to the processor via the INT pin (pin 10). The INT pin can be configured to operate as either push-pull or open drain, and its polarity (active high or active low) is also selectable. All of these interrupt latches have an individual enable/clear register and an individual interrupt mask register associated with them.
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Rising edge of CT_C8 occurring after this limit will trigger an interrupt (if enabled).
CT_C8_(A/B)
Expected Delay (Approx. 125 ns)
Late Allowance (35 ns)
Figure 4. CT_C8_A and CT_C8_B Error Detection 4.17 GPIO Ports Four general purpose input/output ports are provided. The ports may be individually configured to a variety of modes and can also be used as interrupt sources. Possible uses of the GPIO ports would be controlling H.100/H.110 termination switches or implementing the SCbus CLKFAIL signal. 4.18 Message Channel The ML53612 provides a complete interface between the CT_MC CT Bus signal and a local HDLC controller. This includes generation of MC_CLK as well as buffering of MC_TXD and MC_RXD. 4.19 Law/Linear Conversion & Gain Law/Linear conversion and/or gain are selected independently per time-slot. The following conversions are supported: * * * * * * A to to A A to Linear to Linear Linear to Linear to A
A to and to A conversions are G.711 compliant (when "No gain" is selected). Gain may be selected over a range of 31 dB in 1dB steps. When conversion or gain is selected there will be an additional 1 frame (125 ms) delay through the device. To minimize delay, channels that do not require conversion or gain may by-pass the conversion and gain circuitry.
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5.0 REGISTERS
5.1 Microprocessor Address Map
With Direct Parallel Access Disabled (C_[96] = 0) (Default)
A_[2:0] 7h 6h 5h 4h 3h 2h 1h 0h Reserved Data Register 2 (DR_2) Data Register 1 (DR_1) Data Register 0 (DR_0) Reserved Address Register 1 (AR_1) Address Register 0 (AR_0) Command/Status Register Register
With Direct Parallel Access Enabled (C_[96] = 1)
A_[9:0] FFh:C0h BFh:80h 7Fh:08h 07h 06h 05h 04h 03h 02h 01h 00h Direct Receive Switch Parallel Access Ch. 63:0 Direct Transmit Switch Parallel Access Ch. 63:0 Reserved Reserved Data Register 2 (DR_2) Data Register 1 (DR_1) Data Register 0 (DR_0) Reserved Address Register 1 (AR_1) Address Register 0 (AR_0) Command/Status Register Register
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5.2 Command/Status Register
D_[7:0] 0 1 2 3 4 5 6 7 Busy (Read Only) Read Command (Write Only) Write Command (Write Only) Terminate Command (Write Only) Reserved Reserved Reserved Reset (Read/Write) Definition
Busy (D_0) (Read Only)
This bit is set ("1") when a Command that requires synchronization with the ML53612's internal state machine has been initiated, and cleared ("0") when the command has been completed. For Commands that do not require synchronization this bit is always clear ("0"). The following commands require synchronization: * Routing Memory Write command * In-Direct Parallel Access Read or Write command
Read (D_1) (Write Only)
Setting this bit ("1") initiates a synchronized read of the register pointed to by the Address Register. When the Busy bit is clear ("0"), the contents of the register to be read are available by reading the Data Register. It is NOT necessary to clear ("0") this bit after it has been set ("1").
Note: For "Reads" that do not require synchronization (all "Reads" except In-Direct Parallel Access Read) it is not necessary to set this bit. The Data Registers can be read immediately after writing the Address Register.
Write (D_2) (Write Only)
Setting this bit ("1") initiates a write of the register pointed to by the Address Register. It is NOT necessary to clear ("0") this bit after it has been set ("1").
Terminate (D_3) (Write Only)
Setting this bit ("1") terminates a command that requires synchronization with the ML53612's internal state machine. The command in process is completed asynchronously and the Busy bit is cleared. It is NOT necessary to clear ("0") this bit after it has been set ("1").
Reset (D_7) (Read/Write)
Setting this bit ("1") resets the ML53612 and initializes the Configuration and Routing Registers. This command is analogous to the function of the RESET pin. Clearing this bit ("0") returns the ML53612 to normal operation, ready to be configured.
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5.3 Internal Address Map [1] [2]
AR 0014h:0000h 00ffh:00fch 1007h:1000h 203fh:2000h 303fh:3000h 403fh:4000h 503fh:5000h 603fh:6000h 703fh:7000h Configuration Device ID Stream Switch Routing Ch. 7:0 Transmit Switch Routing Ch. 63:0 Receive Switch Routing Ch. 63:0 Indirect Transmit Switch Parallel Access Ch. 63:0 Indirect Receive Switch Parallel Access Ch. 63:0 Transmit Switch Conversion Ch. 63:0 Receive Switch Parallel Conversion Ch. 63:0 Register
1. AR is the concatenation of AR_1 and AR_0. 2. All other locations reserved (Read-back = 00, Write has no effect).
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5.4 Configuration Registers Note: All "Reserved" configuration registers should be written "0".
Configuration Register Byte 0, AR = 0000h
DR_0 0 1 2 3 [7:4] C 0 1 2 3 [7:4] Diagnostic Mode Test Mode APLL Power-down Mode APLL Bypass Mode APLL CLKREF Frequency [3:0] Definition
Diagnostic Mode (C_ [0]) (Read/Write)
Set to 0 for normal operation 0 1 Diagnostic Mode Disabled Diagnostic Mode Enabled (Default)
Test Mode (C_ [1]) (Read/Write)
Enables testing with the slave DPLL bypassed. Set to 0 for normal operation. 0 1 Test Mode Disabled (Default) Test Mode Enabled
APLL Power-down Mode (C_ [2]) (Read/Write)
Powers down analog PLL, resets APLL charge pump. Set to 0 for normal operation. 0 1 APLL Power-down Mode Disabled APLL Power-down Mode Enabled (Default)
APLL Bypass Mode (C_ [3]) (Read/Write)
APLL Bypass used during simulation and testing. Set to 0 for normal operation. 0 1 APLL Bypass Mode Disabled APLL Bypass Mode Enabled (Default)
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APLL CLKREF Frequency [3:0] (C_ [7:4]) (Read/Write)
Put APLL in Power-down (C_[2] = 1) when changing APLL CLKREF Frequency. 0h 1h 2h 3h 4h 5h 6h 7h 8h 9h Ah Bh Ch Dh Eh Fh 65.536 MHz (32 X 2.048 MHz) (Default) 49.152 MHz (24 X 2.048 MHz) 32.768 MHz (16 X 2.048 MHz) 16.384 MHz (8 X 2.048 MHz) 8.192 MHz (4 X 2.048 MHz) 4.096 MHz (2 X 2.048 MHz) 2.048 MHz Reserved 49.408 MHz (32 X 1.544 MHz) 37.056 MHz (24 X 1.544 MHz) 24.704 MHz (16 X 1.544 MHz) 12.352 MHz (8 X 1.544 MHz) 6.176 MHz (4 X 1.544 MHz) 3.088 MHz (2 X 1.544 MHz) 1.544 MHz 1.536 MHz
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Configuration Register Byte 1, AR = 0001h
DR_0 [1:0] 2 3 4 5 6 7 C [9:8] 10 11 12 13 14 15 Slave Bus Mode [1:0] Slave Local Timing Source Select Advance Slave PLL Timing Slave CT Manual/Auto Mode Slave CT A/B Select Slave CT A/B Read-back Reserved Definition
Slave Bus Mode [1:0] (C_ [9:8]) (Read/Write) [1]
00 01 10 11 CT Bus - Slave to CT_C8 & CT_FRAME (see Slave CT A/B Select) (Default) SCbus - Slave to SCLK & FR_COMP MVIP - Slave to C2 & FR_COMP Local - Slave to L_CLK & L_FS (see Slave Local Timing Source Select)
1. When local slave mode is selected, L_CLK frequency, polarity and output enable, and L_FS polarity, position and output enable must be configured accordingly.
Slave Local Timing Source Select (C_ [10]) (Read/Write)
0 1 L_CLK_0, L_FS_0 (Default) L_CLK_1, L_FS_1
Advance Slave PLL Timing (C_ [11]) (Read/Write)
The slave PLL timing may be advanced one 7.6 ns period to compensate for delay. Set to 0 for normal operation. 0 1 Advance Slave PLL Timing Disabled (Default) Advance Slave PLL Timing Enabled
Slave CT Manual/Auto Mode (C_ [12]) (Read/Write) [1]
0 1 Slave CT Manual Mode (Default) Slave CT Auto Mode
1. In auto mode, slave will only switch when an error exists on the current signal set and NOT on the other signal set.
Slave CT A/B Select (C_ [13]) (Read/Write)
Select signal set in manual mode then switch to auto. 0 1 CT A Select (Default) CT B Select
Slave CT A/B Read-back (C_ [14]) (Read Only)
0 1 CT A Selected CT B Selected
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Configuration Register Byte 2, AR = 0002h
DR_0 0 1 2 3 4 5 6 7 C 16 17 18 19 20 21 22 23 Master CT Enable Master CT A/B Select Reserved Advance Master PLL Timing Master Manual/Auto Mode Master Primary/Secondary Select Master Primary/Secondary Read-back Reserved Definition
Master CT Enable (C_ [16]) (Read/Write)
Enables the Master PLL to drive the CT Bus. 0 1 Master Disabled (Default) Master Enabled
Master CT A/B Select (C_ [17]) (Read/Write) [1]
Selects the signal set driven by the Master PLL. 0 1 CT_C8_A & CT_FRAME_A (Default) CT_C8_B & CT_FRAME_B
1. When in Secondary Master mode, the signal set (A or B) NOT selected here is used as the reference.
Advance Master PLL Timing (C_ [19]) (Read/Write)
When operating as secondary master, the master PLL timing may be advanced one 7.6 ns clock period to compensate for delay. Set to 0 for normal operation. 0 1 Advance Master PLL Timing Disabled (Default) Advance Master PLL Timing Enabled
Master Manual/Auto Mode (C_ [20]) (Read/Write) [1]
0 1 Master Manual Mode (Default) Master Auto Mode
1. Master Auto mode allows Secondary Master to become Primary if an error occurs on the reference signal set. To switch back to Secondary Master it is necessary to go into manual mode.
Master Primary/Secondary Select (C_ [21]) (Read/Write)
0 1 Primary Master Select (Default) Secondary Master Select
Master Primary/Secondary Read-back (C_ [22]) (Read Only)
0 1 Primary Master Selected Secondary Master Selected
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Configuration Register Byte 3, AR = 0003h
DR_0 [1:0] 2 3 4 5 6 7 C [25:24] 26 27 28 29 30 31 SCbus SCLK Frequency [1:0] SCbus Master Enable - SCLK, SCLKX2 & FR_COMP Reserved MVIP-90 Master Enable - C2, C4 & FR_COMP H-MVIP Master Enable - C2, C4, C16 & FR_COMP Reserved Reserved Definition
SCbus SCLK Frequency [1:0] (C_ [25:24]) (Read/Write)
00 01 10 11 2.048 MHz (Default) 4.096 MHz 8.192 MHz Reserved
SCbus Master Enable (C_ [26]) (Read/Write)
When enabled as Primary Master, this register enables the SCLK, SCLKX2 & FR_COMP signals to be driven. 0 1 SCbus Master Disabled (Default) SCbus Master Enabled
MVIP-90 Master Enable (C_ [28]) (Read/Write)
When enabled as Primary Master, this register enables the C2, C4 & FR_COMP signals to be driven. 0 1 MVIP-90 Master Disabled (Default) MVIP-90 Master Enabled
H-MVIP Master Enable (C_ [29]) (Read/Write)
When enabled as Primary Master, this register enables the C2, C4, C16 & FR_COMP signals to be driven. 0 1 H-MVIP Master Disabled (Default) H-MVIP Master Enabled
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Configuration Register Byte 4, AR = 0004h
DR_0 [2:0] 3 [5:4] 6 7 C [34:32] 35 [37:36] 38 39 Master PLL Mode [2:0] Reserved Master PLL Mode Read-back [1:0] Condition Master PLL Reference Reserved Definition
Master PLL Mode [2:0] (C_ [34:32]) (Read/Write) [1]
000 001 010 011 100 101 110 111 Normal (Default) Reserved Holdover Free Run Reserved Reserved Auto Normal to Holdover switch on Master PLL error Auto Normal to Free Run switch on Master PLL error
1. Master PLL error occurs when the Master PLL is out of lock with its reference signal. It is necessary to manually select "Normal" to go back to normal operation after an auto switch has occurred.
Master PLL Mode Read-back [1:0] (C_ [37:36]) (Read Only)
00 01 10 11 Normal Reserved Holdover Free Run
Condition Master PLL Reference (C_ [38]) (Read/Write)
When enabled, conditions a change in references for MTIE compatibility. 0 1 Condition Master PLL Reference Disabled (Default) Condition Master PLL Reference Enabled
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Configuration Register Byte 5, AR = 0005h
DR_0 [3:0] 4 [6:5] 7 C [43:40] 44 [46:45] 47 Master PLL Reference Select [3:0] Reserved Master PLL Reference Frequency [1:0] Reserved Definition
Master PLL Reference Select [3:0] (C_ [43:40]) (Read/Write)
0h 1h 2h 3h 4h 5h 6h 7h 8h 9h ah bh ch dh eh fh None (Default) Reserved Reserved Reserved Reserved Reserved CT_NETREF_1 CT_NETREF_2 L_NETREF_0 L_NETREF_1 Reserved Reserved Reserved Reserved Reserved Reserved
Master PLL Reference Frequency [1:0] (C_ [46:45]) (Read/Write)
00 01 10 11 8 kHz (Default) 1.536 MHz 1.544 MHz 2.048 MHz
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Configuration Register Byte 6, AR = 0006h
DR_0 [3:0] 4 [6:5] 7 C [51:48] 52 [54:53] 55 CT_NETREF_1 Source Select [3:0] Reserved CT_NETREF_1 Divider [1:0] CT_NETREF_1 Output Enable Definition
CT_NETREF_1 Source Select [3:0] (C_ [51:48]) (Read/Write)
0h 1h 2h 3h 4h 5h 6h 7h 8h 9h ah bh ch dh eh fh None (Default) Reserved Reserved Reserved Reserved Reserved Reserved Reserved L_NETREF_0 L_NETREF_1 Reserved Reserved Reserved Reserved Reserved Reserved
CT_NETREF_1 Divider [1:0] (C_ [54:53]) (Read/Write)
00 01 10 11 Divide source by 1 (Default) Divide source by 192 Divide source by 193 Divide source by 256
CT_NETREF_1 Output Enable (C_ [55]) (Read/Write)
0 1 CT_NETREF_1 Output Tri-stated (Default) CT_NETREF_1 Output Enabled
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Configuration Register Byte 7, AR = 0007h
DR_0 [3:0] 4 [6:5] 7 C [59:56] 60 [62:61] 63 CT_NETREF_2 Source Select [3:0] Reserved CT_NETREF_2 Divider [1:0] CT_NETREF_2 Output Enable Definition
CT_NETREF_2 Source Select [3:0] (C_ [59:56]) (Read/Write)
0h 1h 2h 3h 4h 5h 6h 7h 8h 9h ah bh ch dh eh fh None (Default) Reserved Reserved Reserved Reserved Reserved Reserved Reserved L_NETREF_0 L_NETREF_1 Reserved Reserved Reserved Reserved Reserved Reserved
CT_NETREF_2 Divider [1:0] (C_ [62:61]) (Read/Write)
00 01 10 11 Divide source by 1 (Default) Divide source by 192 Divide source by 193 Divide source by 256
CT_NETREF_2 Output Enable (C_ [63]) (Read/Write)
0 1 CT_NETREF_2 Output Tri-stated (Default) CT_NETREF_2 Output Enabled
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Configuration Register Byte 8, AR = 0008h
DR_0 0 1 2 3 4 5 6 7 C 64 65 66 67 68 69 70 71 L_CLK_0, L_FS_0 Output Enable L_CLK_1, L_FS_1 Output Enable CT_D_ Output Enable Mode CT_D_DISABLE Output Enable CT_D_DISABLE CT_D_DISABLE On Input CT_D_DISABLE On Error CT_D_DISABLE Read-back Definition
L_CLK_0, L_FS_0 Output Enable (C_ [64]) (Read/Write)
0 1 L_CLK_0, L_FS_0 Output Tri-stated (Default) L_CLK_0, L_FS_0 Output Enabled
L_CLK_1, L_FS_1 Output Enable (C_ [65]) (Read/Write)
0 1 L_CLK_1, L_FS_1 Output Tri-stated (Default) L_CLK_1, L_FS_1 Output Enabled
CT_D_ Output Enable Mode (C_ [66]) (Read/Write)
0 1 CT_D_[31:0] Output Tri-stated before bit cell boundary - Based on H.100/H.110 (Default) CT_D_[31:0] Output Tri-stated at bit cell boundary
CT_D_DISABLE Output Enable (C_ [67]) (Read/Write)
0 1 CT_D_DISABLE pin Output Tri-stated (Default) CT_D_DISABLE pin Output Enabled
CT_D_DISABLE (C_ [68]) (Read/Write)
0 1 CT_D_ Outputs Enabled (Default) CT_D_ Outputs Disabled
CT_D_DISABLE On Input (C_ [69]) (Read/Write)
0 1 CT_D_DISABLE On Input Disabled (Default) CT_D_DISABLE On Input Enabled
CT_D_DISABLE On Error (C_ [70]) (Read/Write)
0 1 CT_D_DISABLE On Error Disabled (Default) CT_D_DISABLE On Error Enabled
CT_D_DISABLE Read-back (C_ [71]) (Read Only)
0 1 CT_D_ Outputs Enabled CT_D_ Outputs Disabled
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Configuration Register Byte 9, AR = 0009h
DR_0 [1:0] [3:2] 4 5 [7:6] C [73:72] [75:74] 76 77 [79:78] L_SI_[1:0], L_SO_[1:0] Stream Rate [1:0] L_CLK_0 Frequency [1:0] L_CLK_0 Polarity L_FS_0 Polarity L_FS_0 Position [1:0] Definition
L_SI_[1:0], L_SO_[1:0] Stream Rate [1:0] (C_ [73:72]) (Read/Write)
00 01 10 11 2.048 Mbps (L_SI_[1:0], L_SO_[1:0]) (Default) 4.096 Mbps (L_SI_[0], L_SO_[0]) 8.192 Mbps (L_SI_[0], L_SO_[0]) Reserved
L_CLK_0 Frequency [1:0] (C_ [75:74]) (Read/Write) [1]
00 01 10 11 2.048 MHz (Default) 4.096 MHz 8.192 MHz 16.384 MHz
1. Note: the L_CLK_0 frequency need not match the L_SI and L_SO stream frequencies, neither need it match the CT_C8 frequency when configured as slave-to-CT.
L_CLK_0 Polarity (C_ [76]) (Read/Write)
0 1 L_CLK_0 Non-Inverted (Default) L_CLK_0 Inverted
L_FS_0 Polarity (C_ [77]) (Read/Write)
0 1 L_FS_0 Non-Inverted (Default) L_FS_0 Inverted
L_FS_0 Position [1:0] (C_ [79:78]) (Read/Write)
00 01 10 11 Early - L_FS_0 occurs during the last L_CLK_0 period of the frame (Default) Straddle - L_FS_0 straddles the frame boundary Late - L_FS_0 occurs during the first L_CLK_0 period of the frame Reserved
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Configuration Register Byte 10, AR = 000ah
DR_0 [1:0] [3:2] 4 5 [7:6] C [81:80] [83:82] 84 85 [87:86] Reserved L_CLK_1 Frequency [1:0] L_CLK_1 Polarity L_FS_1 Polarity L_FS_1 Position [1:0] Definition
L_CLK_1 Frequency [1:0] (C_ [83:82]) (Read/Write)
00 01 10 11 2.048 MHz (Default) 4.096 MHz 8.192 MHz 16.384 MHz
L_CLK_1 Polarity (C_ [84]) (Read/Write)
0 1 L_CLK_1 Non-Inverted (Default) L_CLK_1 Inverted
L_FS_1 Polarity (C_ [85]) (Read/Write)
0 1 L_FS_1 Non-Inverted (Default) L_FS_1 Inverted
L_FS_1 Position [1:0] (C_ [87:86]) (Read/Write)
00 01 10 11 Early - L_FS_1 occurs during the last L_CLK_1 period of the frame (Default) Straddle - L_FS_1 straddles the frame boundary Late - L_FS_1 occurs during the first L_CLK_1 period of the frame Reserved
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Configuration Register Byte 11, AR = 000bh
DR_0 [1:0] [3:2] [5:4] [7:6] C [89:88] [91:90] [93:92] [95:94] CT_D_[3:0] Data Stream Rate [1:0] CT_D_[7:4] Data Stream Rate [1:0] CT_D_[11:8] Data Stream Rate [1:0] CT_D_[15:12] Data Stream Rate [1:0] Definition
CT_D_[3:0] Data Stream Rate [1:0] (C_ [89:88]) (Read/Write)
00 01 10 11 2.048 Mbps 4.096 Mbps 8.192 Mbps (Default) Reserved
CT_D_[7:4] Data Stream Rate [1:0] (C_ [91:90]) (Read/Write)
00 01 10 11 2.048 Mbps 4.096 Mbps 8.192 Mbps (Default) Reserved
CT_D_[11:8] Data Stream Rate [1:0] (C_ [93:92]) (Read/Write)
00 01 10 11 2.048 Mbps 4.096 Mbps 8.192 Mbps (Default) Reserved
CT_D_[15:12] Data Stream Rate [1:0] (C_ [95:94]) (Read/Write)
00 01 10 11 2.048 Mbps 4.096 Mbps 8.192 Mbps (Default) Reserved
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Configuration Register Byte 12, AR = 000ch
DR_0 0 1 2 3 4 5 6 7 C 96 97 98 99 100 101 102 103 Direct Parallel Access Enable Microprocessor Watchdog Enable APLL Clock Watchdog Enable Reserved Message Channel Registered TXD Enable Message Channel Output Disable Reserved Reserved Definition
Direct Parallel Access Enable (C_ [96]) (Read/Write)
0 1 Direct Parallel Access disabled (Default) Direct Parallel Access enabled
Microprocessor Watchdog Enable (C_ [97]) (Read/Write)
When enabled, the ML53612 enters into reset after the Analog PLL clocks for 256mS ( 50%). Each time C_[97] is cleared (0) and then set (1), the microprocessor watchdog count is reset. 0 1 Microprocessor Watchdog disabled (Default) Microprocessor Watchdog enabled
APLL Clock Watchdog Enable (C_ [98]) (Read/Write)
When enabled, C_[98] will read back as being set (1) until the Analog PLL clocks for 125 S ( 50%), then will read back as being cleared (0). Each time C_[98] is cleared (0) and then set (1), the clock watchdog count is reset. 0 1 APLL Clock Watchdog disabled (Default) APLL Clock Watchdog enabled
Message Channel Registered TXD Enable (C_ [100]) (Read/Write)
0 1 MC_TXD passed though to CT_MC (Default) MC_TXD registered to CT_MC on rising edge of MC_CLK
Message Channel Output Disable with Loop-back (C_ [101]) (Read/Write)
When CT_MC output is disabled, the local message channel circuitry can be tested without disturbing the CT Bus. 0 1 CT_MC Output enabled (Default) CT_MC Output Tri-stated, MC_TXD looped back to MC_RXD
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Configuration Register Byte 13, AR = 000dh
DR_0 0 1 2 3 4 5 6 7 C 104 105 106 107 108 109 110 111 INT Polarity INT Mask INT Output Driver Configuration INT Reserved Reserved Reserved Reserved Definition
INT Polarity (C_ [104]) (Read/Write)
0 1 INT Active Low (Default) INT Active High
INT Mask (C_ [105]) (Read/Write)
0 1 INT Unmasked INT Masked (Default)
INT Output Driver Configuration (C_ [106]) (Read/Write)
0 1 Open Drain (Default) Push-Pull
INT (C_ [107]) (Read Only)
This register is the logical or of all unmasked interrupt sources. 0 1 All unmasked interrupts false Any unmasked interrupt true
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Configuration Register Byte 14, AR = 000eh [1]
DR_0 0 1 2 3 4 5 6 7 C 112 113 114 115 116 117 118 119 CT Bus A Error Interrupt Mask CT Bus B Error Interrupt Mask SCbus Error Interrupt Mask MVIP Error Interrupt Mask Master PLL Error Interrupt Mask Frame Boundary Interrupt Mask Reserved Reserved Definition
1. Masking an interrupt disables that interrupt from being OR'ed together with other interrupts to the INT pin. The state of the latches are accessible while masked (polling mode).
CT Bus A Error Interrupt Mask (C_ [112]) (Read/Write)
0 1 CT Bus A Error Interrupt Unmasked CT Bus A Error Interrupt Masked (Default)
CT Bus B Error Interrupt Mask (C_ [113]) (Read/Write)
0 1 CT Bus B Error Interrupt Unmasked CT Bus B Error Interrupt Masked (Default)
SCbus Error Interrupt Mask (C_ [114]) (Read/Write)
0 1 SCbus Error Interrupt Unmasked SCbus Error Interrupt Masked (Default)
MVIP Error Interrupt Mask (C_ [115]) (Read/Write)
0 1 MVIP Error Interrupt Unmasked MVIP Error Interrupt Masked (Default)
Master PLL Error Interrupt Mask (C_ [116]) (Read/Write)
0 1 Master PLL Error Interrupt Unmasked Master PLL Error Interrupt Masked (Default)
Frame Boundary Interrupt Mask (C_ [117]) (Read/Write)
0 1 Frame Boundary Interrupt Unmasked Frame Boundary Interrupt Masked (Default)
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Configuration Register Byte 15, AR = 000fh
DR_0 0 1 2 3 4 5 6 7 C 120 121 122 123 124 125 126 127 CT Bus A Error Latch Clear CT Bus B Error Latch Clear SCbus Error Latch Clear MVIP Error Latch Clear Master PLL Error Latch Clear Frame Boundary Latch Clear Reserved Reserved Definition
CT Bus A Error Latch Clear (C_ [120]) (Read/Write)
0 1 CT Bus A Error Latch Enabled CT Bus A Error Latch held clear (Default)
CT Bus B Error Latch Clear (C_ [121]) (Read/Write)
0 1 CT Bus B Error Latch Enabled CT Bus B Error Latch held clear (Default)
SCbus Error Latch Clear (C_ [122]) (Read/Write)
0 1 SCbus Error Latch Enabled SCbus Error Latch held clear (Default)
MVIP Error Latch Clear (C_ [123]) (Read/Write)
0 1 MVIP Error Latch Enabled MVIP Error Latch held clear (Default)
Master PLL Error Latch Clear (C_ [124]) (Read/Write)
0 1 Master PLL Error Latch Enabled Master PLL Error Latch held clear (Default)
Frame Boundary Latch Clear (C_ [125]) (Read/Write)
0 1 Frame Boundary Latch Enabled Frame Boundary Latch held clear (Default)
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Configuration Register Byte 16, AR = 0010h
DR_0 0 1 2 3 4 5 6 7 C 128 129 130 131 132 133 134 135 CT Bus A Error Latch CT Bus B Error Latch SCbus Error Latch MVIP Error Latch Master PLL Error Latch Frame Boundary Latch Reserved Reserved Definition
CT Bus A Error Latch (C_ [128]) (Read Only)
0 1 CT Bus A Error Latch False CT Bus A Error Latch True
CT Bus B Error Latch (C_ [129]) (Read Only)
0 1 CT Bus B Error Latch False CT Bus B Error Latch True
SCbus Error Latch (C_ [130]) (Read Only)
0 1 SCbus Error Latch False SCbus Error Latch True
MVIP Error Latch (C_ [131]) (Read Only)
0 1 MVIP Error Latch False MVIP Error Latch True
Master PLL Error Latch (C_ [132]) (Read Only)
0 1 Master PLL Error Latch False Master PLL Error Latch True
Frame Boundary Latch (C_ [133]) (Read Only)
0 1 Frame Boundary Latch False Frame Boundary Latch True
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Configuration Register Byte 17, AR = 0011h
DR_0 0 1 2 3 4 5 6 7 C 136 137 138 139 140 141 142 143 GPIO_0 Input GPIO_0 Output GPIO_0 Output Enable GPIO_0 Output Driver Configuration GPIO _0 Latch Polarity GPIO _0 Interrupt Mask GPIO _0 Latch Clear GPIO _0 Latch Definition
GPIO_0 Input (C_ [136]) (Read Only)
0 1 GPIO_0 Input = 0 GPIO_0 Input = 1
GPIO_0 Output (C_ [137]) (Read/Write)
0 1 GPIO_0 Output = 0 (Default) GPIO_0 Output = 1
GPIO_0 Output Enable (C_ [138]) (Read/Write)
0 1 GPIO_0 Output Tri-stated (Default) GPIO_0 Output Enabled
GPIO_0 Output Driver Configuration (C_ [139]) (Read/Write)
0 1 Open Drain (Default) Push-Pull
GPIO _0 Latch Polarity (C_ [140]) (Read/Write)
0 1 GPIO _0 Latch set when GPIO_0 input = 0 (Default) GPIO _0 Latch set when GPIO_0 input = 1
GPIO _0 Interrupt Mask (C_ [141]) (Read/Write)
0 1 GPIO _0 Interrupt Unmasked GPIO _0 Interrupt Masked (Default)
GPIO _0 Latch Clear (C_ [142]) (Read/Write)
0 1 GPIO _0 Latch Enabled GPIO _0 Latch held clear (Default)
GPIO _0 Latch (C_ [143]) (Read Only)
0 1 GPIO _0 Latch False GPIO _0 Latch True
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Configuration Register Byte 18, AR = 0012h
DR_0 0 1 2 3 4 5 6 7 C 144 145 146 147 148 149 150 151 GPIO_1 Input GPIO_1 Output GPIO_1 Output Enable GPIO_1 Output Driver Configuration GPIO _1 Latch Polarity GPIO _1 Interrupt Mask GPIO _1 Latch Clear GPIO _1 Latch Definition
GPIO_1 Input (C_ [144]) (Read Only)
0 1 GPIO_1 Input = 0 GPIO_1 Input = 1
GPIO_1 Output (C_ [145]) (Read/Write)
0 1 GPIO_1 Output = 0 (Default) GPIO_1 Output = 1
GPIO_1 Output Enable (C_ [146]) (Read/Write)
0 1 GPIO_1 Output Tri-stated (Default) GPIO_1 Output Enabled
GPIO_1 Output Driver Configuration (C_ [147]) (Read/Write)
0 1 Open Drain (Default) Push-Pull
GPIO _1 Latch Polarity (C_ [148]) (Read/Write)
0 1 GPIO _1 Latch set when GPIO_1 input = 0 (Default) GPIO _1 Latch set when GPIO_1 input = 1
GPIO _1 Interrupt Mask (C_ [149]) (Read/Write)
0 1 GPIO _1 Interrupt Unmasked GPIO _1 Interrupt Masked (Default)
GPIO _1 Latch Clear (C_ [150]) (Read/Write)
0 1 GPIO _1 Latch Enabled GPIO _1 Latch held clear (Default)
GPIO _1 Latch (C_ [151]) (Read Only)
0 1 GPIO _1 Latch False GPIO _1 Latch True
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Configuration Register Byte 19, AR = 0013h
DR_0 0 1 2 3 4 5 6 7 C 152 153 154 155 156 157 158 159 GPIO_2 Input GPIO_2 Output GPIO_2 Output Enable GPIO_2 Output Driver Configuration GPIO _2 Latch Polarity GPIO _2 Interrupt Mask GPIO _2 Latch Clear GPIO _2 Latch Definition
GPIO_2 Input (C_ [152]) (Read Only)
0 1 GPIO_2 Input = 0 GPIO_2 Input = 1
GPIO_2 Output (C_ [153]) (Read/Write)
0 1 GPIO_2 Output = 0 (Default) GPIO_2 Output = 1
GPIO_2 Output Enable (C_ [154]) (Read/Write)
0 1 GPIO_2 Output Tri-stated (Default) GPIO_2 Output Enabled
GPIO_2 Output Driver Configuration (C_ [155]) (Read/Write)
0 1 Open Drain (Default) Push-Pull
GPIO _2 Latch Polarity (C_ [156]) (Read/Write)
0 1 GPIO _2 Latch set when GPIO_2 input = 0 (Default) GPIO _2 Latch set when GPIO_2 input = 1
GPIO _2 Interrupt Mask (C_ [157]) (Read/Write)
0 1 GPIO _2 Interrupt Unmasked GPIO _2 Interrupt Masked (Default)
GPIO _2 Latch Clear (C_ [158]) (Read/Write)
0 1 GPIO _2 Latch Enabled GPIO _2 Latch held clear (Default)
GPIO _2 Latch (C_ [159]) (Read Only)
0 1 GPIO _2 Latch False GPIO _2 Latch True
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Configuration Register Byte 20, AR = 0014h
DR_0 0 1 2 3 4 5 6 7 C 160 161 162 163 164 165 166 167 GPIO_3 Input GPIO_3 Output GPIO_3 Output Enable GPIO_3 Output Driver Configuration GPIO _3 Latch Polarity GPIO _3 Interrupt Mask GPIO _3 Latch Clear GPIO _3 Latch Definition
GPIO_3 Input (C_ [160]) (Read Only)
0 1 GPIO_3 Input = 0 GPIO_3 Input = 1
GPIO_3 Output (C_ [161]) (Read/Write)
0 1 GPIO_3 Output = 0 (Default) GPIO_3 Output = 1
GPIO_3 Output Enable (C_ [162]) (Read/Write)
0 1 GPIO_3 Output Tri-stated (Default) GPIO_3 Output Enabled
GPIO_3 Output Driver Configuration (C_ [163]) (Read/Write)
0 1 Open Drain (Default) Push-Pull
GPIO _3 Latch Polarity (C_ [164]) (Read/Write)
0 1 GPIO _3 Latch set when GPIO_3 input = 0 (Default) GPIO _3 Latch set when GPIO_3 input = 1
GPIO _3 Interrupt Mask (C_ [165]) (Read/Write)
0 1 GPIO _3 Interrupt Unmasked GPIO _3 Interrupt Masked (Default)
GPIO _3 Latch Clear (C_ [166]) (Read/Write)
0 1 GPIO _3 Latch Enabled GPIO _3 Latch held clear (Default)
GPIO _3 Latch (C_ [167]) (Read Only)
0 1 GPIO _3 Latch False GPIO _3 Latch True
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5.5 Device ID Registers (Read Only)
Device ID byte 3, AR = 00ffh
DR_0 [7:4] [3:0] Version [3:0] Part Number [15:12] Definition
Device ID byte 2, AR = 00feh
DR_0 [7:0] Part Number [11:4] Definition
Device ID byte 1, AR = 00fdh
DR_0 [7:4] [3:0] Part Number [3:0] Manufacturer ID [10:7] Definition
Device ID byte 0, AR = 00fch
DR_0 [7:1] [0] Manufacturer ID [6:0] 0 = Device does not support Boundary Scan 1 = Device supports Boundary Scan Definition
Note: Device ID byte [3:0] for the MG73Q011-181TC (engineering sample) = 00 6c 00 5dh
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5.6 Stream Switch Routing Registers, AR = 1007h:1000h (Ch. 7:0) Note: To ensure compatibility with possible future versions of this device, write "0" to all "Reserved" bits in the routing registers. All "Reserved" routing registers read-back "0".
DR_0 [4:0] [7:5] Input Data Stream [4:0] Reserved (write zero) Definition
Input Data Stream [4:0] (Read/Write)
00h 01h 02h * * 1eh 1fh DR_1 [4:0] [6:5] 7 Output Data Stream [4:0] Reserved (write zero) Output Enable CT_D_[0] (Default) CT_D_[1] CT_D_[2] * * CT_D_[30] CT_D_[31] Definition
Output Data Stream [4:0] (Read/Write)
00h 01h 02h * * 1eh 1fh CT_D_[0] (Default) CT_D_[1] CT_D_[2] * * CT_D_[30] CT_D_[31]
Output Enable (Read/Write)
0 1 Output Disabled (Default) Output Enabled
DR_2 [1:0] [7:2] Partition [1:0] Reserved (write zero)
Definition
Partition [1:0] (Read/Write) Selects which time-slots are used when rate conversion is taking place. See the following table for a description of the partition function.
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5.7 Stream Switch Connection Mapping
Input Data Stream Rate 2 Mbps Output Data Stream Rate 2 Mbps 4 Mbps Partition 0 0 1 8 Mbps 0 1 2 3 4 Mbps 2 Mbps 0 1 4 Mbps 8 Mbps 0 0 1 8 Mbps 2 Mbps 0 1 2 3 4 Mbps 0 1 8 Mbps 0 Time-Slot Connection 0 to 1, 1 to 2, 2 to 3, ... , 31 to 0 0 to 2, 1 to 4, 2 to 6, ... , 31 to 0 0 to 3, 1 to 5, 2 to 7, ... , 31 to 1 0 to 4, 1 to 8, 2 to 12, ... , 31 to 0 0 to 5, 1 to 9, 2 to 13, ... , 31 to 1 0 to 6, 1 to 10, 2 to 14, ... , 31 to 2 0 to 7, 1 to 11, 2 to 15, ... , 31 to 3 0 to 1, 2 to 2, 4 to 3, ... , 62 to 0 1 to 1, 3 to 2, 5 to 3, ... , 63 to 0 0 to 1, 1 to 2, 2 to 3, ... , 63 to 0 0 to 2, 1 to 4, 2 to 6, ... , 63 to 0 0 to 3, 1 to 5, 2 to 7, ... , 63 to 1 0 to 1, 4 to 2, 8 to 3, ... , 124 to 0 1 to 1, 5 to 2, 9 to 3, ... , 125 to 0 2 to 1, 6 to 2, 10 to 3, ... , 126 to 0 3 to 1, 7 to 2, 11 to 3, ... , 127 to 0 0 to 1, 2 to 2, 4 to 3, ... , 126 to 0 1 to 1, 3 to 2, 5 to 3, ... , 127 to 0 0 to 1, 1 to 2, 2 to 3, ... , 127 to 0
Frame Boundary CT_D time-slots @ 8 Mbps CT_D time-slots @ 4 Mbps CT_D time-slots @ 2 Mbps 123 123 30 124 62 31 125 126 63 127 0 0 0 1 2 1 3 4 2 1
Figure 5. CT Bus Data Stream Switching The Stream Switch provides a data stream-to-data stream connection capability. Switching between any of the 32 CT Bus data streams operating at 2, 4, or 8 Mbps is supported. Eight stream switch channels are provided. Individual time-slots are not tri-state controlled. Buffering is done on single time-slots rather than entire frames. This trade-off complicates the connection matrix, but without this compromise it would not be practical to implement the Stream Switch. Depending upon the data stream rates, the stream switch provides a minimum of 256 and a maximum of 1024 uni-directional time-slot connections. Stream switches in other ML53612 devices in a system may be used simultaneously to increase switching capability. The output of the stream switch is multiplexed with the output of the transmit switch, with the transmit switch having priority.
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The main application of the Stream Switch is to provide an inter-rate exchange highway allowing legacy Bus devices operating at different rates to exchange data. A typical configuration of the Stream Switch using 2 switch channels and 3 streams to provide 32 full duplex connections between SCbus (operating at 4 MHz) and MVIP is outlined below. Example: Stream switch channel 0 is configured with CT_D_0 as the input data stream and the even time-slots (partition = 0) of CT_D_8 as the output data stream. Stream switch channel 1 is configured with the odd time-slots (partition = 1) of CT_D_8 as the input data stream and CT_D_1 as the output data stream.
CT_D _0 (MVIP) CT_D _1 (MVIP) CT_D _8 (SCbus)
31
0 0 63 0 1 2
1 1 3 4 2
Figure 6. Data Stream Switching Example
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5.8 Transmit Switch Routing Registers, AR = 203fh:2000h (Ch. 63:0) Note: To ensure compatibility with subsequent versions of this device, write "0" to all "Reserved" bits in the routing registers. All "Reserved" routing registers read-back "0".
DR_0 [6:0] 7 Output Time-slot Reserved (write zero) Definition
Output Time-slot [6:0] (Read/Write)
Selects the CT_D time-slot for transmit channel routing. 00h 01h 02h * * 7eh 7fh Time-slot 0 (Default) Time-slot 1 Time-slot 2 * * Time-slot 126 Time-slot 127
Note: Internally all time-slots run at 8 Mbps. To transmit on CT_D data streams running at a slower rate, use the following conversion: If CT_D data stream is operating at 4 Mbps, transmit switch output time-slot = CT_D time-slot X 2. If CT_D data stream is operating at 2 Mbps, transmit switch output time-slot = CT_D time-slot X 4.
DR_1 [4:0] [6:5] 7 Output Data Stream Reserved (write zero) Output Enable Definition
Output Data Stream [4:0] (Read/Write)
Selects the CT_D Data stream for transmit channel routing. 00h 01h 02h * * 1eh 1fh CT_D_[0] (Default) CT_D_[1] CT_D_[2] * * CT_D_[30] CT_D_[31]
Output Enable (Read/Write)
Controls the Output Enable for the selected CT Bus data stream and time-slot. 0 1 Output Disabled (Default) Output Enabled
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DR_2 0 1 2 [7:3] Delay CT Bus Connect Source Reserved (write zero)
Definition
Delay (Read/Write)
Selects the switching delay mode. When set to Constant, data is switched on frame boundaries resulting in a constant 1 frame delay and allowing "bundling". When set to Minimum, data is switched on 2 Mbps time-slot boundaries reducing the delay through the switch for certain combinations of input to output time-slots. 0 1 Constant (Default) Minimum
Note: Do not use Minimum delay mode on channels using parallel data source. CT Bus Connect Enable (Read/Write)
Enables the switch to be used for CT Bus to CT Bus connection without externally connecting L_SO to L_SI. When enabled, the L_SI input is replaced by the corresponding L_SO output. CT Bus connect allows inter-operability switching to be provided by any unused transmit and receive switch pair. 0 1 CT Bus Connect Disabled (Default) CT Bus Connect Enabled
Note: 1. When CT Bus Connect is enabled, the L_SO to L_SI connection does not pass through the conversion circuitry. See Figure 2. 2. The Receive Switch Output Enable register does not have to be set to make this connection. Source (Read/Write)
Selects the transmit channel data source. When set to 0, Serial TDM data from L_SI or L_SO (see CT Bus Connect Enable) is selected. When set to 1, the corresponding parallel access register is selected as the source of the transmit channel data. 0 1 Serial TDM data (Default) Parallel microprocessor data
Note: The Serial TDM data and the parallel access register share common registers within the transmit switch. Therefore it is necessary to write to the parallel access register after the source is changed to parallel microprocessor data.
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5.9 Receive Switch Routing Registers, AR = 303fh:3000h (Ch. 63:0) Note: To ensure compatibility with subsequent versions of this device, write "0" to all "Reserved" bits in the routing registers. All "Reserved" routing registers read-back "0".
DR_0 [6:0] 7 Input Time-slot Reserved (write zero) Definition
Input Time-slot [6:0] (Read/Write)
Selects the CT_D time-slot for receive channel routing. 00h 01h 02h * * 7eh 7fh Time-slot 0 (Default) Time-slot 1 Time-slot 2 * * Time-slot 126 Time-slot 127
Note: Internally all time-slots run at 8 Mbps. To receive from CT_D streams running at a slower rate, use the following conversion: If CT_D stream is operating at 4 Mbps, receive switch input time-slot register = CT_D time-slot X 2 + 1. If CT_D stream is operating at 2 Mbps, receive switch input time-slot register = CT_D time-slot X 4 + 3.
DR_1 [4:0] [6:5] 7 Input Data Stream Reserved (write zero) Output Enable Definition
Input Data Stream [4:0] (Read/Write)
Selects the CT_D data stream for receive channel routing. 00h 01h 02h * * 1eh 1fh CT_D_[0] (Default) CT_D_[1] CT_D_[2] * * CT_D_[30] CT_D_[31]
Output Enable (Read/Write)
Controls the Output Enable for the channel's local stream. 0 1 Output Disabled (Default) Output Enabled
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DR_2 0 1 2 [7:3] Delay Local Connect Source Reserved (write zero)
Definition
Delay (Read/Write)
Selects the switching delay mode. When set to Constant, data is switched on frame boundaries resulting in a constant 1 frame delay and allowing "bundling". When set to Minimum, data is switched on 2 Mbps time-slot boundaries reducing the delay through the switch for certain combinations of input to output time-slots. 0 1 Constant (Default) Minimum
Note: Do not use Minimum delay mode on channels using parallel data source. Local Connect Enable (Read/Write)
Enables the receive switch to be used for local connection. When enabled, a transmit channel is connected to a receive channel without using the CT Bus. 0 1 Local Connect Disabled (Default) Local Connect Enabled
Note: When Local Connect is Enabled, the Receive Switch routing registers DR_0 is redefined as the 6 bits of the transmit channel number instead of the CT_D time-slot, as shown below:
DR_0_[5:0] Transmit channel bits [5:0]
Source (Read/Write)
Selects the receive channel data source. When set to 0, Serial TDM data from the CT Bus data stream or transmit channel (see Local Connect Enable) is selected. When set to 1, the channels parallel access register is selected as the source of the receive channel data. 0 1 Serial TDM data (Default) Parallel microprocessor data
Note: The Serial TDM data and the parallel access register share common registers within the receive switch. Therefore it is necessary to write to the parallel access register after the source is changed to parallel microprocessor data.
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5.10 Indirect Transmit Switch Parallel Access Registers, AR = 403fh:4000h (Ch. 63:0)
DR_0 [7:0] TDM Data [1:8] Definition
TDM Data [1:8] (Read/Write)
Writing to this register provides the transmit data when the transmit switch channel is configured to use parallel microprocessor data as its source (to CT_D). This register and the serial input buffer share common hardware, therefore this register must be written after the transmit switch channel source is changed from serial TDM data to parallel microprocessor data. The transmit switch channel output buffer data obtained by reading the TDM data register. When the transmit switch channel is configured to use serial TDM data as its source, the data from the local SI channel can be monitored. When the transmit switch channel is configured to use parallel microprocessor data as its source, the data written into this register can be monitored.
Note: When converted from parallel to serial, TDM Data Bit 1 is transmitted first. 5.11 Indirect Receive Switch Parallel Access Registers, AR = 503fh:5000h (Ch. 63:0)
DR_0 [7:0] TDM Data [1:8] Definition
TDM Data [1:8] (Read/Write)
Writing to this register provides the receive data when the receive switch channel is configured to use parallel microprocessor data as its source (to L_SO). This register and the serial input buffer share common hardware, so this register must be written after the receive switch channel source is changed from serial TDM data to parallel microprocessor data. The receive switch channel output buffer data is obtained by reading the TDM Data register. When the receive switch channel is configured to use serial TDM data as its source, the data from the CT_D stream and time-slot selected in the receive switch routing registers can be monitored. When the receive switch channel is configured to use parallel microprocessor data as its source, the data written into this register can be monitored.
Note: When converted from parallel to serial, TDM Data Bit 1 is transmitted first.
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5.12 Transmit Switch Conversion Registers, AR = 603Fh:6000h (Ch. 63:0) Receive Switch Conversion Registers, AR = 703Fh:7000h (Ch. 63:0) To ensure compatibility with possible future versions of this device all "Reserved" Conversion registers should be written "0". All "Reserved" Conversion registers read-back "0".
DR_0 [5:0] [7:6] Gain Reserved Definition
Gain [5:0] (Read/Write) Selects the gain of a channel.
1Fh 1Eh 1Dh . . 03h 02h 01h 00h 20h 21h 22h 23h . . 3Dh 3Eh 3Fh -29 dB -30 dB -31 dB +3 dB +2 dB +1 dB No gain (Default) Idle ( = 7f, A = d5, Linear = 8000) -1 dB -2 dB -3 dB +31 dB +30 dB +29 dB
Note: Gain settings do not apply when Mode is By-pass.
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Even # Channels DR_1 [3:0] [7:4] Definition Mode Reserved DR_1 [2:0] [7:3]
Odd # Channels Definition Mode Reserved
Mode [3:0] (Read/Write) 00xx 0100 0101 0110 0111 1000 1001 1010 1011 11xx By-pass (Default) A to A to A to to A A to Linear to Linear Linear to Linear to A Linear to Linear 0xx 100 101 110 111
Mode [2:0] (Read/Write) By-pass (Default) A to A to A to to A
Note: Linear Conversions require two consecutive channels. When an Even numbered Channel is configured for Linear Conversion, the configuration registers of the next higher Odd numbered Channel are "don't care". When A/ to Linear conversion is selected, the A/ data is taken from the even numbered channel. When Linear to A/ conversion is selected, the A/ data is presented on the even numbered channel. Linear data (16 bit - sign/magnitude) is formatted MSB in the even channel, LSB in the odd channel.
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6.0 ELECTRICAL SPECIFICATIONS
6.1 Absolute Maximum Ratings
Parameter Storage Temperature Power Supply Voltage Input Voltage TS VPS VI Symbol Test Conditions Min -65 -0.3 -0.3 Max 150 4.6 6 Unit C V V
6.2 Recommended Operating Conditions
Parameter Ambient Temperature Supply Voltage TA VDD Symbol Test Conditions Min -40 3.0 Max 85 3.6 Unit C V
6.3 DC Electrical Characteristics
Parameter Core Supply Current I/O Supply Current Analog PLL Supply Current Input High Voltage Input Low Voltage Schmitt Input High Voltage Schmitt Input Low Voltage Schmitt Input Hysteresis Voltage Output High Voltage - PCI Output Low Voltage - PCI Output High Voltage - 24mA Output Low Voltage - 24mA Output High Voltage - 8mA Output Low Voltage - 8mA Output High Voltage - 6mA Output Low Voltage - 6mA 50 k Pull-up Current I/O Leakage Current Symbol IDDC IDDO IDDA VIH VIL Vt+ VtVHYS VOH-PCI VOL-PCI VOH-24mA VOL-24mA VOH-8mA VOL-8mA VOH-6mA VOL-6mA IP ILI/O IOH = -2 mA IOL = 6 mA IOH = -24 mA IOL = 24 mA IOH = -8 mA IOL = 8 mA IOH = -6 mA IOL = 6 mA VPAD = 0 V VI/O = VDD or VSS -15 2.4 0.4 -170 10 2.4 0.4 2.4 0.4 Test Conditions VDDC = 3.6V VDDO = 3.6V VDDA = 3.6V 2.0 -0.5 2.05 -0.5 0.4 2.4 0.55 Min Max 125 140 10 5.5 0.8 5.5 0.7 Unit mA mA mA V V V V V V V V V V V V V A A
NOTES: 1. PCI Drivers meet the AC Specifications for the PCI 5V signaling environment. 2. Pin Capacitance: Input pins = 6 pF, Output pins = 9 pF, Bi-directional pins = 10 pF.
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6.4 AC Electrical Characteristics Note: Signals ending in "_N" are active low. Microprocessor Interface Timing - Intel Bus Mode, Non-multiplexed Address [1] [2] [3]
Parameter CS_N setup to WR_N WR_N pulse width A_[9:0] setup to WR_N (C_96=1) A_[2:0] setup to WR_N (C_96=0) A_[9:0] hold from WR_N D_[7:0] setup to WR_N D_[7:0] hold from WR_N D_[7:0] float to valid delay from CS_N RD_N, and A_[9:0] D_[7:0] valid to float delay from CS_N or RD_N 1. Timing measured with 100 pF load on D_[7:0]. 2. Write cycle may be controlled by CS_N or WR_N. 3. ALE=1. t1 t2 t3 t4 t5 t6 t7 t8 t9 Symbol Min 40 40 5 40 5 40 5 0 0 50 10 Typ Max Unit ns ns ns ns ns ns ns ns ns
t1 CS_N
RD_N
t2 WR_N t3 t4 A_[9:0] t5
t6 D_[7:0]
t7
t8
t9
Figure 7. Microprocessor Interface Timing - Intel Bus Mode, Non-multiplexed Address
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Microprocessor Interface Timing - Motorola Bus Mode, Non-multiplexed Address [1] [2] [3]
Parameter CS_N setup to STRB_N STRB_N pulse width R/W_N setup to STRB_N R/W_N hold from STRB_N A_[9:0] setup to STRB_N (C_96=1) A_[2:0] setup to STRB_N (C_96=0) A_[9:0] hold from STRB_N D_[7:0] setup to STRB_N D_[7:0] hold from STRB_N D_[7:0] float to valid delay from CS_N, STRB_N, and A_[9:0] D_[7:0] valid to float delay from CS_N or STRB_N 1. Timing measured with 100 pF load on D_[7:0]. 2. Write cycle may be controlled by CS_N or STRB_N. 3. AS=1. t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 Symbol Min 40 40 5 5 5 40 5 40 5 0 0 50 10 Typ Max Unit ns ns ns ns ns ns ns ns ns ns ns
t1 CS_N
t2 STRB_N
t3 R/W_N t5 t6 A_[9:0] t7
t4
t3
t4
t8 D_[7:0]
t9
t10
t11
Figure 8. Microprocessor Interface Timing - Motorola Bus Mode, Non-multiplexed Address
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Microprocessor Interface Timing - Multiplexed Address
Parameter ALE (AS) pulse width A_[9:0] setup to ALE (AS) A_[9:0] hold from ALE (AS) t1 t2 t3 Symbol Min 20 5 5 Typ Max Unit ns ns ns
t1 ALE (AS) t2 t3 A_[9:0]
Figure 9. Microprocessor Interface Timing - Multiplexed Address Reset Timing
Parameter RESET pulse width t1 Symbol Min 50 Typ Max Unit ns
t1 RESET
Figure 10. Reset Timing
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]
Local Clock and Frame Synchronization Timing [1] [2]
Parameter L_CLK period (2.048 MHz) L_CLK period (4.096 MHz) L_CLK period (8.192 MHz) L_CLK period (16.384 MHz) L_FS delay from L_CLK _ (Early position) L_FS delay from L_CLK _ (Straddle position) L_FS delay from L_CLK _ (Late position) Symbol t1a t1b t1c t1d t2 t3 t4 -10 -10 -10 Min Typ 488 244 122 61 +10 +10 +10 Max Unit ns ns ns ns ns ns ns
1. Timing measured with 100 pF load on all Local bus outputs. 2. L_CLK and L_FS shown with positive polarity, timing is equivalent when signals are inverted.
Local Clock to CT Bus Clock Skew [1]
Parameter With C_11 (Advance Slave DPLL Timing) set to 0 (default) With C_11 (Advance Slave DPLL Timing) set to 1 Symbol t5 t5 Min Typ Max +22.5 / -0 +15 / -7.5 Unit Ns Ns
1. When reference L_CLK is more stable, there is no reduction in the amplitude of the skew, but a reduction in the number of occurrences. The further away from the center frequency, the more frequently the skew occurs. The skew amplitude will jump in steps, but the range will remain the same. Test conditions were 65.536 MHz (C_[7:4]= 0) and 2.048 MHz (C_[7:4] = 6).
Local Serial Stream Timing [1]
Parameter L_SO float to valid delay from Bit Cell Boundary L_SO valid to valid delay from Bit Cell Boundary L_SO valid to float delay from Bit Cell Boundary 2,048Mb/s Sample Point from Bit Cell Boundary 4,096Mb/s Sample Point from Bit Cell Boundary 8.192Mb/s Sample Point from Bit Cell Boundary L_SI Setup to Sample Point L_SI Hold to Sample Point Symbol t6 t7 t8 t9a t9b t9c t10 t11 10 10 Min -10 -10 -10 +335.5 +213.5 +91.5 Typ Max +10 +10 +10 Unit ns ns ns ns ns ns ns ns
1. The Bit Cell Boundary is defined by the relative edge of L_CLK (Figure 11 assumes that L_CLK and L_FS polarities are both non-inverted (C_[76] = 0; C_[77] = 0; C_[84] = 0; C_[85] = 0))
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Frame Boundary (Bit Cell Boundary)
t5 CT_C8_A/B Bit Cell Boundary t1 L_CLK Bit Cell Boundary Bit Cell Boundary
t2 L_FS
t2
t3 L_FS t4 L_FS
t3
t4
t6 L_SO_[7:0] t9 t10 L_SI_[7:0] t11
t7
t8
Figure 11. Local Clock and Frame Synchronization Timing
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H.100/H.110 Clock Alignment (Extract from H.100/H.110 Specifications, Rev. 1.0)
CT_FRAME_(A/B)_N
CT_C8_(A/B)
FR_COMP_N
C16 _N
C2
C4 _N
SCLK (2.048 MHz)
SCLK x2* (2 x 2.048MHz)
SCLK (4.096MHz)
SCLK x2* (2 x 4.096MHz)
SCLK (8.192MHz)
SCLK x2* (2 x 8.192MHz)
Note: C16_N, C2, and C4_N not defined in H.110.
Figure 12. H.100/H.110 Clock Alignment
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H.100/H.110 Frame Structure (Extract from H.100/H.110 Specifications, Rev. 1.0)
125 S CT_FRAME _(A/B)_N
CT_C8_(A/B)
CT_Dx
8
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
1
Time-Slot
0
127
Figure 13. H.100/H.110 Frame Structure H.100/H.110 Detailed Data Bus Timing (Extract from H.100/H.110 Specifications, Rev. 1.0)
1 Bit Cell Tfs CT_FRAME _(A/B)_N Tfp Tc8h CT_C8_(A/B) Tc8p Tdoz Data Out Ts 127 Bit 8 Tzdo Ts 0 Bit 1 Tdiv Tdv Data In Tsamp 1.4V Tdod 2.4V 0.4V Tc8I 2.0V 0.6V Tfh 2.0V 0.6V
Figure 14. H.100/H.110 Detailed Data Bus Timing
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6.5 H.100/H.110 Bus Timing Specification (Extract from H.100/H.110 Specifications, Rev. 1.0)
Parameter Clock edge rate (All Clocks) CT_C8_(A/B) and CT_FRAME_(A/B)_N edge rate CT_NETREF edge rate Clock CT_C8_(A/B) Period Clock CT_C8_(A/B) High Time H.100 H.110 Clock CT_C8_(A/B) Low Time H.100 H.110 Data Sample Point Data Output to HiZ Time H.100 H.110 Data HiZ to Output Time H.100 H.110 Data Output Delay Time H.100 H.110 Data Valid Time H.100 H.110 Data Invalid Time H.100 H.110 CT_FRAME_(A/B)_N Width CT_FRAME_(A/B)_N Setup Time CT_FRAME_(A/B)_N Hold Time Phase Correction 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. Tfp Tfs Tfh Tdiv Tdv Tdod Tzdo Tsamp Tdoz -20 -10 0 0 0 0 0 0 102 102 90 45 45 0 122 Tc8l H.100 H.110 H.110 Tc8p Tc8h 122.066- 49- 63- 49- 63- 90 0 0 22 11 22 11 69 83 112 112 180 90 90 10 Symbol Min 0.25 0.25 Typ Max 2 2 0.3 122.074+ 73+ 69+ 73+ 69+ Unit V/ns V/ns V/ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
[17] [15] [16] [1] [1]
Notes
[2] [3] [4] [4] [5] [4] [4] [5] [6] [7] [8] [9] [8] [9] [10] [7] [8] [9] [8] [9] [10] [7] [8] [8] [10] [7] [11] [12] [11] [13] [14]
The rise and fall times are determined by the edge rate in V/nS. A maximum edge rate is the fastest rate at which a clock transitions. 10% - 90%. Test Load = 150 pF. Tc8p Min and Max are under free-run conditions assuming 32 ppm clock accuracy. Non-cumulative, Tc8p requirements still need to be met. Duty Cycle measured at transmitter under no load conditions. For reference only Test Load - 200 pF Measured at the transmitter. Tdoz and Tzdo apply at every time-slot boundary. Test Load - 12 pF Measured at the receiver. Reference only: Tdv = Max. clock cable delay + Max. data cable delay + Max. data HiZ to output time = 12nS + 35nS + 22 nS = 69nS. Max. clock cable delay and max. data cable delay are worst case numbers based on electrical simulation. Reference only: Tdv = Max. clock backplane delay + Max. data backplane delay + Max. data HiZ to output time = 26nS + 46nS + 11nS = 83nS. Max. clock delay and max. data delay are worst case numbers based on electrical simulation. Based on worst case electrical simulation. This range accounts for (Phase Correction). Tcell = Max. clock backplane delay + Max. data backplane delay + Max. Tzdo + (Min. Tdiv - Max. Tdv) + Max Tdoz + F = 26nS + 46nS + 11nS + (102nS - 83nS) + 10nS + 10nS = 122nS. Max. clock delay and max. data delay are worst case numbers based on electrical simulation.
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17. (Phase Correction) results from PLL timing corrections.
H.100. Measuring conditions:
Data lines
Vth (threshold voltage) = 1.4V Vhi (test high voltage) = 2.4V Vlo (test low voltage) = 0.4V Input signal edge rate = 1 V/nS
Clock and Frame lines
Vt+ (test high voltage) = 2.0V Vt- (test low) = 0.6V Input signal edge rate = 1 V/nS
H.110. Measuring conditions:
Data lines
Vhi (test high voltage) = 2.0V Vlo (test low voltage) = 0.8V Input signal edge rate = 1 V/nS
Clock and Frame lines
Vt+ (test high voltage) = 2.0V Vt- (test low voltage) = 0.6V Input signal edge rate = 1 V/nS
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6.6 Clock Skew Requirements (Extract from H.100/H.110 Specifications, Rev. 1.0)
Parameter (H.100) Max Skew between CT_C8 "A" and "B" (H.110) Max Skew between CT_C8 "A" and "B" (H.100) Max Skew between CT_C8_A and any compatibility clock (H.110) Max Skew between CT_C8_A and any compatibility clock Symbol Tskc8 Tskc8 Tskcomp Tskcomp Min Typ Max 10 10 5 5 Unit ns ns ns ns Notes
[1] [2] [3] [4] [2] [3] [4] [5] [1]
[5]
1. Test Load - 200 pF. 2. Assumes "A" and "B" masters in adjacent slots. 3. When static skew is 10nS and, in the same clock cycle, each clock performs a 10nS phase correction in opposite directions, a maximum skew of 30nS will occur during that clock cycle. 4. Meeting the skew requirements in Table 2 and the requirements of Section 2.3 (in the H.100/H.110 Specifications, Rev. 1.0) could require the PLL's generating CT_C8 to have different time constants when acting as primary and secondary clock masters. 5. Test Load - "A" load = "B" load.
CT_C8_A
Vt+
CT_C8_A
Vt+
Tskc8 CT_C8_B Vt+ Inter-operability Clocks Vt+ Vt-
Tskcomp
Tskcomp
Figure 15. Clock Skew Requirements
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7.0 ML53612 PACKAGE SPECIFICATIONS
7.1 LQFP176 Package Outlines and Dimensions
132
89
1.25 TYP
133
88
26.0 0.2 sq. 24.0 0.1 sq.
1.0 0.2
176
45
0 ~ 10 1.7 MAX. 1.4 0.05 0 ~ 0.2 0.25 0.5 TYP 0.6 0.15
1 1.25 TYP 0.5 Index Mark Mirror Finish 0.17 0.05
0.22 0.05
44 0.10
M
0.10
Seating Plane
All measurements are in millimeters or degrees
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7.2 LQFP176 Mounting Pad Reference Measurements
0.5 0.25
24.4
1.0 24.4
LQFP176-P-2424-0.50-BK
All measurements are in millimeters
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The information contained herein can change without notice owing to product and/or technical improvements. Please make sure before using the product that the information you are referring to is up-to-date. The outline of action and examples of application circuits described herein have been chosen as an explanation of the standard action and performance of the product. When you actually plan to use the product, please ensure that the outside conditions are reflected in the actual circuit and assembly designs. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters outside the specified maximum ratings or operation outside the specified operating range. Neither indemnity against nor license of a third party's industrial and intellectual property right,etc.is granted by us in connection with the use of product and/or the information and drawings contained herein. No responsibility is assumed by us for any infringement of a third party's right which may result from the use thereof. When designing your product, please use our product below the specified maximum ratings and within the specified operating ranges, including but not limited to operating voltage, power dissipation, and operating temperature. The products listed in this document are intended for use in general electronics equipment for commercial applications (e.g.,office automation, communication equipment, measurement equipment, consumer electronics, etc.).These products are not authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property or death or injury to humans. Such applications include, but are not limited to: traffic control, automotive, safety, aerospace, nuclear power control, and medical, including life support and maintenance. Certain parts in this document may need governmental approval before they can be exported to certain countries. The purchaser assumes the responsibility of determining the legality of export of these parts and will take appropriate and necessary steps, at their own expense, for export to another country. Copyright 2000 Oki Semiconductor; Copyright 2000 Dialogic Corporation. This document may not, in whole or in part, be reproduced, stored in a retrieval system, translated, or transmitted in any form or by any means, electronic or mechanical, without the express written consent of Dialogic Corporation or Oki Semiconductor. This document contains preliminary information that is subject to change without notice. While every effort has been made to ensure the accuracy of this document, due to ongoing improvements and revisions neither Dialogic nor Oki Semiconductor can guarantee the accuracy of printed material after the date of publication, nor can they accept responsibility for errors or omissions. Dialogic and Oki Semiconductor reserve the right to make changes to the product(s) described, or information contained herein, as needed. Neither Dialogic Corporation nor Oki Semiconductor guarantees the suitability of the product(s) described for any particular implementation. Nor does either company accept responsibility for any loss or damage of whatever nature resulting from the use of, or reliance upon, the information contained herein. Dialogic is a registered trademark, and CT612, SCSA, SCxbus, and the Signal Computing System Architecture are trademarks of Dialogic Corporation. CT Bus is a trademark of the Enterprise Computer Telephony Forum (ECTF). CompactPCI is a registered trademark of the PCI Industrial Computers Manufacturers Group (PICMG). MVIP and MVIP-90 are trademarks of Natural MicroSystems. All other names, products, and services are the trademarks or registered trademarks of their respective organizations. Oki Semiconductor reserves the right to make changes in specifications at anytime and without notice. This information furnished by Oki Semiconductor in this publication is believed to be accurate and reliable. However, no responsibility is assumed by Oki Semiconductor for its use; nor for any infringements of patents or other rights of third parties resulting from its use. No license is granted under any patents or patent rights of Oki.
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